1. Technical Field
The present invention relates generally to semiconductor devices and more particularly to a method for optimizing the current-carrying and/or shielding capabilities of wide wires.
2. Related Art
In semiconductor applications, aluminum wires are often designed to be very wide, particularly in those instances where high current or electrical shielding is needed. Copper wires are favored over aluminum wires because of copper's higher conductivity and reliability. However, very wide copper wires are difficult to produce because the common manufacturing finishing process, i.e., chemical mechanical polishing (CMP), dishes the copper wire.
Two approaches have been taken to solve this problem: a) constraint of linewidths and pattern densities during circuit design, and b) filling of a fraction of the metal from the centers of very wide copper wires with dielectric studs, which is oftentimes referred to as ‘cheesing’.
The first approach forces designers to grapple with the linewidth and pattern density limitations of copper CMP directly. Maximum linewidth and wide-line/wide-space rules combined with maximum local density rules require designers to manually adjust a large variety of high-current, sensitive, and/or analog circuits so as to avoid metallization layouts that are known to be unmanufacturable in copper. The specific limits of the manufacturing process and the form of these rules vary from generation to generation and from manufacturer to manufacturer. As a result, it is difficult for designers to both automate and optimize the layout of wide copper features. This approach is also problematic for semiconductor manufacturers because different customers often find very different ways to work around these constraints. One advantage of this approach, however, is that it is possible to obtain layouts that satisfy all of the constraints of copper CMP and maximize the current-carrying and/or shielding capability of the circuit.
The second approach shifts the burden of accommodating the limitations of the copper CMP process from the designers to an automation tool. There are a number of benefits to this approach: a designer can use a simple layout because linewidth and pattern-density limitations are largely or completely eliminated; the resulting layout is manufacturable and reliable; and the effects of the automated treatment on the final electrical behavior of the layout are straightforward and predictable. However, layouts resulting from this approach are less efficient than the hand-tuned layouts of the first approach. This inefficiency derives from the requirement that the automated treatments must be robust for all possible current flows through a circuit without any prior knowledge of the current vectors that are possible during operation of the semiconductor device. That is, the effect of the automated treatment must be completely or nearly isotropic with regard to current flow. For example, referring to FIG. 1, a prior art device 10 is shown comprising a copper wire 20 having a horizontal portion 22 and a vertical portion 24. Along a length of each portion 22, 24 are cut square equiaxial hole shapes 40. Hole shapes 40 are not placed where they would obstruct a non-redundant via, but may be allowed to impinge upon a via that is part of a large redundant array.
Current flow in both a longitudinal direction 50 and a transverse direction 60 is decreased by “current crowding” (the need of current lines to bend around hole shapes 40), to approximately the same degree. That is, the effect of the automated treatment is isotropic with respect to current flow. Such an arrangement permits automated removal of portions of wire 20 without knowledge of any branching of or interconnects with wire 20. However, along longer uninterrupted and unbranched lengths of wire, the accommodation of current flow in the transverse direction is not only unnecessary, but undesirable.
In view of the foregoing, there is a need in the art for a method of providing hole shapes in wide copper wires that increases current flow along the wire's longitudinal axis while decreasing current flow along the wire's transverse axis.